The present invention relates to a semiconductor memory process, and more specifically, to a DRAM capacitor and a method of fabricating the same.
The computer and the electronic industry demand of increasing its whole speed performance as well as it""s cost down for fabricating integrated circuits. As far as a computer is concern, Doubtlessly, the DRAM integrated circuits play a crucial role for a computer is concerned. A great number of DRAM memory cells are usually required, and thus they play a vital factor for determining the I/O speed of the computer. Hence, pursuing the miniaturization of the DRAM device so as to down the cost as well as high-speed performance are almost the ultimate goals.
No matter to miniaturize the device or to pursue the high-speed performance, the DRAM cell""s storage capacity is a major factor that needs to be considered. The capacitor is formed with a storage node, a cell plate, and an intervening dielectric layer. Thus the storage capacity could be increased by making the capacitor dielectric thinner, by using an insulator with a larger dielectric constant, or by increasing the area of the capacitor. The first two options are not viable, since capacitor dielectrics thinner than those now being used in DRAM cells will suffer leakage due to Fowler-Nordheim tunneling. The suffering from a higher leakage for using a larger dielectric constant insulator is also reported in some research. Thus, for one-transistor DRAM, a large surface area of the storage node and cell plate are necessary in order to provide high capacitance and therefore optimal performance of the capacitor. However, a large surface area of the storage node and cell plate conflicts with the shrinkage of the feature size of the DRAM.
Balanced against this need is the competing requirement that the capacitor also occupy a minimum of space on the semiconductor substrate on which the capacitor is formed. One manner in which the semiconductor industry has approached minimal space capacitor formation is to form the capacitor at a significant distance above the semiconductor substrate. When so doing, the storage node and the cell plate are typically wrapped around the other, forming what is known as a stacked capacitor.
However, by using a conventional method, the aspect ratio of the contact hole for forming such a stacked capacitor, tends to gradually increase in accordance with the use of three dimensional capacitor structures in the vertical direction. The decrease of the contact-hole diameter and its high aspect ratio impose a large burden on succeeding photolithography steps. If the photolithography is carried out without accurate alignment, the contact hole cannot be formed at a desired site. Also, in the case of a high aspect ratio, it is likely that the etching process of the contact hole will cease before the interlayer insulation film is entirely removed.
A method of forming a contact plug has been proposed to reduce difficulties due to the high aspect ratio of contact holes in storage electrodes. See U.S. Pat. No. 5,332,685, entitled xe2x80x9cMethod of Manufacturing a DRAM Cell,xe2x80x9d to Park et al. Recently, Samsung had proposed using the concept of xe2x80x98landing padxe2x80x99 which has greatly improved the art. See IEDM""94, p635, Kang et al., xe2x80x9cHighly Manufacturable Process Technology for Reliable 256 Mbit and 1 Gbit DRAMs.xe2x80x9d This method increases several mask steps required for fabrication, thereby increasing process complexity. Another improving method is proposed by Liu et al., in U.S. Pat. No. 5,780,339, entitled xe2x80x9cMethod for fabricating a semiconductor memory cell in a DRAM.xe2x80x9d Liu utilizes an inter plug technique and nitride sidewall spacers 30 to improve deep node contact etching damage and reduce the number of mask steps for typical landing pad processes. Thus, Liu""s method allows the manufacture of a semiconductor memory cell that reduces the difficulties due to the high aspect ratio of the contact hole of a storage node. See FIG. 1.
However, to fabricate a DRAM capacitor in Liu""s method, two mask layers are still required for forming the storage node contact and storage node. In addition, didn""t fully utilize the two dielectric layers 22 and 28, and thus the issue of the topology height still exist for making large area of capacitor.
Consequently, an improved method is needed to overcome the above-discussed problems.
An object of the invention provides a method for fabricating a DRAM cell. The invention use bit line, nitride cap, nitride spacer and landing pad to avoid the usage of mask layer of storage node contact and to fully utilize space of IPD1 and IPD2. Furthermore, the mask layer of storage node becomes non-critical.
The other object of the invention is to reduce the topographic height for a DRAM cell.
The method comprises following steps: at first, provide a semiconductor upon which words lines, isolation regions, word line spacers, source/drain regions, word line nitride caps are formed. After that, a self-aligned contact method is used to form slim isolation regions on the tops of word lines so as to define the openings for forming landing pads. The landing pads are to use for storage nodes and bit line contact. A first interpoly dielectric (IPD 1) is then formed on all regions. Then, after bit lines are formed, a nitride cap and a nitride spacer formations are sequentially formed on the tops and the sidewalls of the bit lines.
Subsequently, a second interpoly dielectric layer (IPD 2) is formed. The IPD1 and IPD2 in the invention need to carefully select so that the IDP 2 layer has a substantially higher etching rate than that of IPD1 in a condition that the etchant is properly chosen. Next, line masks is formed on the IPD2 to define the storage nodes. Each line mask is properly disposed so that the open space between two line-masks is in width smaller than the landing pad. A dry etching is then performed to expose portions of the landing pads by etching through the IPD2 and IPD1 using the line masks, the nitride cap, nitride spacers as masks. After tripping the line masks, an isotropic etching to expand the upper portion of recessed regions is achieved. To achieve the goal, in an embodiment, the IPD 2 is formed of BPSG and the IPD1 is made of densified TEOS. The ratio of etching rate for IPD2 (BPSG) to IPD1 (densified TEOS) is about 100:1 to 300:1 by using an etchant such as an anhydrous vapor HF.
After that, an first in-situ doped (ISD1) polysilicon is formed to serve as the capacitor storage node. A photoresist then refill the remnant portions of recessed regions. CMP process is then to planar surface by removing portions of the ISD polysilicon and IPD2 layer using the nitride cap as a stopping layer. Finally, after the photoresist is stripped, a conformal thinner insulating layer and another ISD polysilicon is sequentially formed on the ISD1 polysilicon.